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FTEDA
2006
137views more  FTEDA 2006»
13 years 4 months ago
Statistical Performance Modeling and Optimization
As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing process...
Xin Li, Jiayong Le, Lawrence T. Pileggi
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 1 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
TCAD
2008
172views more  TCAD 2008»
13 years 4 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
13 years 10 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
13 years 11 months ago
Guiding Circuit Level Fault-Tolerance Design with Statistical Methods
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
Drew C. Ness, David J. Lilja