11 search results - page 1 / 3 » Statistical gate delay model considering multiple input swit... |
DAC
2004
ACM
13 years 8 months ago
2004
ACM
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
DAC
1996
ACM
13 years 8 months ago
1996
ACM
: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginni...