11 search results - page 2 / 3 » Statistical gate delay model considering multiple input swit... |
ANSS
2003
IEEE
13 years 10 months ago
2003
IEEE
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate a...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract— This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and focused that decap does not necessarily improve a...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
TAMC
2007
Springer
13 years 10 months ago
2007
Springer
In previous work we have introduced an average-case measure for the time complexity of Boolean circuits – that is the delay between feeding the input bits into a circuit and the ...