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ICCAD
2007
IEEE
124views Hardware» more  ICCAD 2007»
14 years 2 months ago
Timing budgeting under arbitrary process variations
Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical ins...
Ruiming Chen, Hai Zhou
DAC
2006
ACM
14 years 6 months ago
Stochastic variational analysis of large power grids considering intra-die correlations
For statistical timing and power analysis that are very important problems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctua...
Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhar...
DAC
1999
ACM
14 years 6 months ago
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 2 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
ICCAD
2003
IEEE
221views Hardware» more  ICCAD 2003»
14 years 2 months ago
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems
Abstract— Dynamic voltage scaling (DVS) is a powerful technique for reducing dynamic power consumption in a computing system. However, as technology feature size continues to sca...
Le Yan, Jiong Luo, Niraj K. Jha