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» Statistical reliability analysis under process variation and...
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ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
DAC
2010
ACM
13 years 9 months ago
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
Lin Huang, Qiang Xu
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
14 years 2 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks
DAC
2008
ACM
14 years 6 months ago
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness
The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires at...
Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao
ICCAD
2006
IEEE
147views Hardware» more  ICCAD 2006»
14 years 2 months ago
Analysis and modeling of CD variation for statistical static timing
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao