38 search results - page 1 / 8 » Statistical timing analysis with two-sided constraints |
TCAD
2008
13 years 4 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
GLVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...