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DFT
2007
IEEE
104views VLSI» more  DFT 2007»
13 years 11 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
ISCAS
2008
IEEE
136views Hardware» more  ISCAS 2008»
13 years 11 months ago
VLSI architecture for data-reduced steering matrix feedback in MIMO systems
Abstract— Beamforming (BF) for multiple-input multipleoutput (MIMO) wireless communications systems can improve the error rate performance by spatial separation of the transmitte...
Christoph Studer, Peter Luethi, Wolfgang Fichtner
DAC
1999
ACM
13 years 9 months ago
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
13 years 11 months ago
MARS-S: Modeling and Reduction of Soft Errors in Sequential Circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
Natasa Miskov-Zivanov, Diana Marculescu
AMC
2005
148views more  AMC 2005»
13 years 5 months ago
Review of model order reduction methods for numerical simulation of nonlinear circuits
In this paper, we reviewed several newly presented nonlinear model order reduction methods, we analyze these methods theoretically and with experiments in detail. We show the prob...
Lihong Feng