13 search results - page 3 / 3 » Subgridding method for speeding up FD-TLM circuit simulation |
ICC
2007
IEEE
13 years 8 months ago
2007
IEEE
With the advance of semiconductor manufacturing, There are many approaches to deal with these problems. EDA, and VLSI design technologies, circuits with even higher Adding discrete...
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...