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» Supply Voltage Degradation Aware Analytical Placement
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ICCD
2005
IEEE
111views Hardware» more  ICCD 2005»
14 years 1 months ago
Supply Voltage Degradation Aware Analytical Placement
Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus...
Andrew B. Kahng, Bao Liu, Qinke Wang
ISPD
2006
ACM
102views Hardware» more  ISPD 2006»
13 years 10 months ago
A faster implementation of APlace
APlace is a high quality, scalable analytical placer. This paper describes our recent efforts to improve APlace for speed and scalability. We explore various wirelength and densi...
Andrew B. Kahng, Qinke Wang
ASPDAC
2007
ACM
88views Hardware» more  ASPDAC 2007»
13 years 8 months ago
Logic and Layout Aware Voltage Island Generation for Low Power Design
Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but...
Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong
DATE
2010
IEEE
170views Hardware» more  DATE 2010»
13 years 9 months ago
Analytical model for TDDB-based performance degradation in combinational logic
With aggressive gate oxide scaling, latent defects in the gate oxide manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred...
Mihir Choudhury, Vikas Chandra, Kartik Mohanram, R...
VLSI
2010
Springer
13 years 3 months ago
Fine-grained post placement voltage assignment considering level shifter overhead
—Multi-Vdd techniques enable application of lower supply voltage levels on cells with timing slacks. New voltage assignment, placement and voltage island partitioning methods are...
Zohreh Karimi, Majid Sarrafzadeh