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ISCAS
2002
IEEE
125views Hardware» more  ISCAS 2002»
13 years 9 months ago
Switching activity estimation of finite state machines for low power synthesis
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
Mikael Kerttu, Per Lindgren, Mitchell A. Thornton,...
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 1 months ago
State re-encoding for peak current minimization
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
ISLPED
1998
ACM
94views Hardware» more  ISLPED 1998»
13 years 9 months ago
Theoretical bounds for switching activity analysis in finite-state machines
- The objective of this paper is to provide lower and upper bounds for the switching activity on the state lines in Finite State Machines (FSMs). Using a Markov chain model for the...
Diana Marculescu, Radu Marculescu, Massoud Pedram
DAC
2004
ACM
13 years 10 months ago
A new state assignment technique for testing and low power
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J....
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 1 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha