8 search results - page 2 / 2 » Switching activity estimation of finite state machines for l... |
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
ICCAD
2010
IEEE
13 years 3 months ago
2010
IEEE
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...