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VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
14 years 5 months ago
A Module Checking Based Converter Synthesis Approach for SoCs
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
Roopak Sinha, Partha S. Roop, Samik Basu
ICCS
2007
Springer
13 years 9 months ago
Building Verifiable Sensing Applications Through Temporal Logic Specification
Abstract. Sensing is at the core of virtually every DDDAS application. Sensing applications typically involve distributed communication and coordination over large self-organized n...
Asad Awan, Ahmed H. Sameh, Suresh Jagannathan, Ana...
IJSSE
2011
127views more  IJSSE 2011»
13 years 10 days ago
A Formal Language for XML Authorisations Based on Answer Set Programming and Temporal Interval Logic Constraints
The Extensible Markup Language is susceptible to security breaches because it does not incorporate methods to protect the information it encodes. Our work presented in this paper f...
Sean Policarpio, Yan Zhang
DAC
2002
ACM
14 years 6 months ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton
AUSAI
2006
Springer
13 years 9 months ago
Hardware Implementation of Temporal Nonmonotonic Logics
Abstract. In order to apply nonmonotonic logics for specifying industrial automation controllers, we define (1) a method to extend atemporal nonmonotonic logics with temporal opera...
Insu Song, Guido Governatori