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DAC
2002
ACM
14 years 5 months ago
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 9 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
13 years 2 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
13 years 11 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
FM
1999
Springer
121views Formal Methods» more  FM 1999»
13 years 9 months ago
Incremental Design of a Power Transformer Station Controller Using a Controller Synthesis Methodology
ÐIn this paper, we describe the incremental specification of a power transformer station controller using a controller synthesis methodology. We specify the main requirements as s...
Hervé Marchand, Mazen Samaan