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DAC
1996
ACM
13 years 10 months ago
Delay Minimal Decomposition of Multiplexers in Technology Mapping
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
Shashidhar Thakur, D. F. Wong, Shankar Krishnamoor...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 9 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
ICIP
2005
IEEE
14 years 7 months ago
Nonparametric wavelet based texture synthesis
This paper presents a new algorithm for synthesising image texture. Texture synthesis is an important process in image postproduction. Previous approaches can be classified as eit...
Claire Gallagher, Anil C. Kokaram
DSD
2010
IEEE
133views Hardware» more  DSD 2010»
13 years 3 months ago
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
Igor Lemberski, Petr Fiser
FPL
2006
Springer
158views Hardware» more  FPL 2006»
13 years 9 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...