6 search results - page 1 / 2 » Synthesis of high-performance packet processing pipelines |
IPPS
2010
IEEE
13 years 3 months ago
2010
IEEE
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
ISSS
1995
IEEE
13 years 8 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...