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» Synthesizing "Verification Aware" Models: Why and ...
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VLSID
2007
IEEE
112views VLSI» more  VLSID 2007»
14 years 5 months ago
Synthesizing "Verification Aware" Models: Why and How?
Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazu...
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
14 years 1 months ago
Practical, fast Monte Carlo statistical static timing analysis: why and how
Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale designs. Monte Carlo methods are universally employed to validate the accuracy of the appr...
Amith Singhee, Sonia Singhal, Rob A. Rutenbar