19 search results - page 2 / 4 » Synthesizing Switching Logic to Minimize Long-Run Cost |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
DATE
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
ACSD
2007
IEEE
13 years 11 months ago
2007
IEEE
We study sensor minimization problems in the context of fault diagnosis. Fault diagnosis consists in synthesizing a diagnoser that observes a given plant and identifies faults in...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
EUROGRAPHICS
2010
Eurographics
14 years 2 months ago
2010
Eurographics
Continuous constrained optimization is a powerful tool for synthesizing novel human motion segments that are short. Graph-based motion synthesis methods such as motion graphs and ...