88 search results - page 2 / 18 » System-Level Modeling of Dynamically Reconfigurable Hardware... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLD...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is MicroBlaze Vanill...
MSE
2003
IEEE
13 years 10 months ago
2003
IEEE
As SoC (System-on-a-chip) methodology emerges, IP (Intellectual Property) development and integration will play a major role in the hightech industry. To prepare for this future t...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...