7 search results - page 2 / 2 » System-Level SRAM Yield Enhancement |
TCAD
2008
13 years 5 months ago
2008
Abstract--In this paper, we present a postsilicon-tuning technique to improve parametric yield of SRAM array using body bias (BB). First, we show that, although parametric failures...
CODES
2010
IEEE
13 years 3 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...