Sciweavers

Share
TCAD
2008

Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias

9 years 1 months ago
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias
Abstract--In this paper, we present a postsilicon-tuning technique to improve parametric yield of SRAM array using body bias (BB). First, we show that, although parametric failures in SRAM are due to local random intradie variations, the parametric failures increase at extreme interdie corners. Next, we show that proper BB can reduce different types of parametric failures. Finally, we show that adaptive application of BB to different dies, based on their interdie corners, reduces the total number of parametric failures in those dies. This helps to repair the faulty dies at different interdie corners, thereby improving SRAM yield. We show that postsilicon-tuning using BB can result in significant yield enhancement for SRAM (8%
Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TCAD
Authors Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
Comments (0)
books