93 search results - page 2 / 19 » System-level memory modeling for bus-based memory architectu... |
SRDS
1998
IEEE
13 years 9 months ago
1998
IEEE
Software-controlled cache prefetching and data forwarding are widely used techniques for tolerating memory latency in shared memory multiprocessors. However, some previous studies...
EUROMICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper addresses the problem of component selection, task assignment and task scheduling for distributed embedded computer systems. Such systems have a large number of constra...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
EIT
2009
IEEE
13 years 11 months ago
2009
IEEE
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then ...