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» System-on-Chip Verification Process Using UML
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UML
2004
Springer
13 years 9 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
DAC
2001
ACM
14 years 5 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
UML
2001
Springer
13 years 9 months ago
A Formal Mapping between UML Static Models and Algebraic Specifications
: There are several reasons to specify UML models in a formal way The most important are to avoid inconsistencies and ambiguities and to do verification and forecasting of system p...
Liliana Favre
UML
2001
Springer
13 years 9 months ago
Formalization of UML-Statecharts
The work presented here is part of a project that aims at the definition of a methodology for developing realtime software systems based on UML. In fact, being relatively easy to ...
Michael von der Beeck
IFM
2010
Springer
152views Formal Methods» more  IFM 2010»
13 years 2 months ago
Specification and Verification of Model Transformations Using UML-RSDS
In this paper we describe techniques for the specification and verification of model transformations using a combination of UML and formal methods. The use of UML 2 notations to s...
Kevin Lano, Shekoufeh Kolahdouz Rahimi