30 search results - page 5 / 6 » Tableaux and Model Checking for Memory Logics |
VLSID
2001
IEEE
14 years 6 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
KBSE
2007
IEEE
14 years 2 days ago
2007
IEEE
A number of researchers have proposed the use of Boolean satisfiability solvers for verifying C programs. They encode correctness checks as Boolean formulas using finitization: ...
DAC
1996
ACM
13 years 10 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
SIGSOFT
2006
ACM
13 years 11 months ago
2006
ACM
Bitwise operations are commonly used in low-level systems code to access multiple data fields that have been packed into a single word. Program analysis tools that reason about s...