172 search results - page 1 / 35 » Techniques for fast circuit simulation applied to power esti... |
ISLPED
1995
ACM
13 years 8 months ago
1995
ACM
We present a transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits. The proposed approach uses s...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...
DATE
1997
IEEE
13 years 9 months ago
1997
IEEE
: In this paper, we present a new dynamic power estimation method that produces accurate power measures at considerably faster run times. The approach uses an enhanced switch-level...
ISLPED
1996
ACM
13 years 9 months ago
1996
ACM
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...