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DAC
1996
ACM
13 years 9 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
TCAD
1998
126views more  TCAD 1998»
13 years 4 months ago
Iterative remapping for logic circuits
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
Luca Benini, Patrick Vuillod, Giovanni De Micheli
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
13 years 9 months ago
Optimal latch mapping and retiming within a tree
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
Joel Grodstein, Eric Lehman, Heather Harkness, Her...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 8 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
13 years 11 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar