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DATE
2003
IEEE
102views Hardware» more  DATE 2003»
13 years 10 months ago
Power Constrained High-Level Synthesis of Battery Powered Digital Systems
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
S. F. Nielsen, Jan Madsen
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 7 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
TVLSI
2008
120views more  TVLSI 2008»
13 years 5 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
AAAI
2007
13 years 7 months ago
Synthesis of Constraint-Based Local Search Algorithms from High-Level Models
The gap in automation between MIP/SAT solvers and those for constraint programming and constraint-based local search hinders experimentation and adoption of these technologies and...
Pascal Van Hentenryck, Laurent D. Michel
EURODAC
1994
IEEE
139views VHDL» more  EURODAC 1994»
13 years 9 months ago
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
: This paper presents an approach to high-level synthesis which is based upon a 0/1 integer programming model. In contrast to other approaches, this model allows solving all three ...
Birger Landwehr, Peter Marwedel, Rainer Dömer