— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-...