7 search results - page 1 / 2 » Test Bus Sizing for System-on-a-Chip |
TC
2002
13 years 4 months ago
2002
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
GECCO
2006
Springer
13 years 8 months ago
2006
Springer
This paper presents an evolutionary algorithm to develop cooperative strategies for power buyers in a deregulated electrical power market. Cooperative strategies are evolved throu...
ARC
2012
Springer
12 years 9 days ago
2012
Springer
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
LCTRTS
2007
Springer
13 years 10 months ago
2007
Springer
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...