37 search results - page 8 / 8 » Test Enrichment for Path Delay Faults Using Multiple Sets of... |
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ITC
1997
IEEE
13 years 9 months ago
1997
IEEE
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...