9 search results - page 2 / 2 » Test Generation for Acyclic Sequential Circuits with Single ... |
DATE
1999
IEEE
13 years 10 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICCAD
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
DATE
1998
IEEE
13 years 10 months ago
1998
IEEE
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
ICCAD
1997
IEEE
13 years 10 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...