61 search results - page 2 / 13 » Test Pattern Generation Under Low Power Constraints |
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
ATS
2000
IEEE
13 years 9 months ago
2000
IEEE
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model a...