64 search results - page 1 / 13 » Test pattern generation for width compression in BIST |
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson ...
ATS
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) based on width compression method. More formally...
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...