80 search results - page 2 / 16 » Testing embedded-core based system chips |
ETS
2006
IEEE
13 years 11 months ago
2006
IEEE
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
ETS
2011
IEEE
12 years 5 months ago
2011
IEEE
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC . The novel feature of the approach is the use an embedde...
ET
2002
13 years 5 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...