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DFT
2004
IEEE
101views VLSI» more  DFT 2004»
13 years 9 months ago
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
Baosheng Wang, Yuejian Wu, André Ivanov
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
13 years 11 months ago
Extending JTAG for Testing Signal Integrity in SoCs
As the technology is shrinking and the working frequency is going into multi gigahertz range, the issues related to interconnect testing are becoming more dominant. Specifically,...
Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nour...
LEGE
2004
169views Education» more  LEGE 2004»
13 years 7 months ago
Building Assessment Web Service from Question Type Learning Objects
In this paper we discuss the TestTool system as an established testing system model, the one that is being used in real educational settings and supports self-assessment as well as...
Vytautas Reklaitis, Kazys Baniulis, Nerijus Auksta...
TAICPART
2006
IEEE
134views Education» more  TAICPART 2006»
13 years 11 months ago
Integration Testing of Components Guided by Incremental State Machine Learning
The design of complex systems, e.g., telecom services, is nowadays usually based on the integration of components (COTS), loosely coupled in distributed architectures. When compon...
Keqin Li 0002, Roland Groz, Muzammil Shahbaz
ET
2002
115views more  ET 2002»
13 years 5 months ago
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki