Sciweavers

465 search results - page 2 / 93
» The Application of Skewed-Associative Memories to Cache Only...
Sort
View
DAC
2012
ACM
11 years 7 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 3 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
13 years 9 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
OTM
2004
Springer
13 years 10 months ago
A Time Predictable Instruction Cache for a Java Processor
Cache memories are mandatory to bridge the growing gap between CPU speed and main memory access time. Standard cache organizations improve the average execution time but are diffi...
Martin Schoeberl
INFOCOM
2005
IEEE
13 years 10 months ago
IPStash: a set-associative memory approach for efficient IP-lookup
—IP-Lookup is a challenging problem because of the increasing routing table sizes, increased traffic, and higher speed links. These characteristics lead to the prevalence of hard...
Stefanos Kaxiras, Georgios Keramidas