This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...