535 search results - page 1 / 107 » The Cache Performance and Optimizations of Blocked Algorithm... |
ASPLOS
1991
ACM
13 years 8 months ago
1991
ACM
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
ISHPC
2003
Springer
13 years 10 months ago
2003
Springer
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
DAC
2010
ACM
13 years 5 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
TC
1998
13 years 5 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...