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» The Complexity of Adding Failsafe Fault-Tolerance
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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
13 years 11 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
13 years 11 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
COMPSAC
2007
IEEE
13 years 8 months ago
Infrastructure Hardening: A Competitive Coevolutionary Methodology Inspired by Neo-Darwinian Arms Races
The world is increasingly dependent on critical infrastructures such as the electric power grid, water, gas, and oil transport systems, which are susceptible to cascading failures...
Travis C. Service, Daniel R. Tauritz, William M. S...