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» The Complexity of Global Constraints
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HPCA
2012
IEEE
12 years 1 months ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 1 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang
SIGCOMM
2012
ACM
11 years 8 months ago
DeTail: reducing the flow completion time tail in datacenter networks
Web applications have now become so sophisticated that rendering a typical page may require hundreds of intra-datacenter flows. At the same time, web sites must meet strict page ...
David Zats, Tathagata Das, Prashanth Mohan, Dhruba...
CVPR
2012
IEEE
11 years 8 months ago
Bag of textons for image segmentation via soft clustering and convex shift
We propose an unsupervised image segmentation method based on texton similarity and mode seeking. The input image is first convolved with a filter-bank, followed by soft cluster...
Zhiding Yu, Ang Li, Oscar C. Au, Chunjing Xu
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
14 years 1 days ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...