74 search results - page 2 / 15 » The Cyclic Wirelength of Trees |
ASPDAC
2012
ACM
12 years 1 months ago
2012
ACM
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
ISPD
2007
ACM
13 years 6 months ago
2007
ACM
In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture plac...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides...
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm constructs a bounded-skew tree (BST)...