867 search results - page 1 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected i...
DAC
2012
ACM
11 years 7 months ago
2012
ACM
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past dec...
ICCD
2001
IEEE
14 years 1 months ago
2001
IEEE
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
ICCD
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper investigates some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in pe...