7 search results - page 1 / 2 » The First Clock Cycle Is A Real BIST |
CSREAESA
2010
13 years 2 months ago
2010
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
SENSYS
2009
ACM
13 years 9 months ago
2009
ACM
A specific application for wastewater monitoring and actuation, called CSOnet, deployed city-wide in a mid-sized US city, South Bend, Indiana, posed some challenges to a time syn...
SENSYS
2005
ACM
13 years 10 months ago
2005
ACM
Radio duty cycling has received significant attention in sensor networking literature, particularly in the form of protocols for medium access control and topology management. Whi...
FPL
2003
Springer
13 years 10 months ago
2003
Springer
Local search methods such as WSAT have proven to be successful for solving SAT problems. In this paper, we propose two host-FPGA (Field Programmable Gate Array) co-implementations,...
TCAD
2010
12 years 11 months ago
2010
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...