27 search results - page 2 / 6 » The Memory Bandwidth Bottleneck and its Amelioration by a Co... |
PLDI
2010
ACM
13 years 10 months ago
2010
ACM
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
HPCA
2000
IEEE
13 years 9 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...