Sciweavers

8 search results - page 1 / 2
» The Potential for Using Thread-Level Data Speculation to Fac...
Sort
View
HPCA
1998
IEEE
13 years 9 months ago
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
J. Gregory Steffan, Todd C. Mowry
IEEEPACT
1999
IEEE
13 years 9 months ago
In Search of Speculative Thread-Level Parallelism
This paper focuses on the problem of how to find and effectively exploit speculative thread-level parallelism. Our studies show that speculating only on loops does not yield suffi...
Jeffrey T. Oplinger, David L. Heine, Monica S. Lam
ASPLOS
2010
ACM
14 years 4 days ago
Speculative parallelization using software multi-threaded transactions
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B....
CGO
2004
IEEE
13 years 9 months ago
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads
Efficient inter-thread value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving value communication ...
Antonia Zhai, Christopher B. Colohan, J. Gregory S...
ASPLOS
1998
ACM
13 years 9 months ago
Data Speculation Support for a Chip Multiprocessor
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
Lance Hammond, Mark Willey, Kunle Olukotun