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» The Scalasca performance toolset architecture
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ASM
2008
ASM
13 years 6 months ago
Using EventB to Create a Virtual Machine Instruction Set Architecture
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine...
Stephen Wright
ACMMSP
2005
ACM
115views Hardware» more  ACMMSP 2005»
13 years 10 months ago
Performance characteristics of MAUI: an intelligent memory system architecture
Combining ideas from several previous proposals, such as Active Pages, DIVA, and ULMT, we present the Memory Arithmetic Unit and Interface (MAUI) architecture. Because the “inte...
Justin Teller, Charles B. Silio Jr., Bruce L. Jaco...
ICSM
2002
IEEE
13 years 9 months ago
Architecture Analysis Tools to Support Evolution of Large Industrial Systems
This paper describes an architecture analysis tool-set supporting the evolutionary improvement of the software architecture of an existing medical imaging system. The toolset has ...
Tobias Rötschke, René L. Krikhaar
BIBE
2007
IEEE
126views Bioinformatics» more  BIBE 2007»
13 years 6 months ago
FPGA Acceleration of Phylogeny Reconstruction for Whole Genome Data
In this paper we describe our design and characterization of a co-processor architecture to accelerate median-based phylogenetic reconstruction for generearrangement data. Our curr...
Jason D. Bakos, Panormitis E. Elenis, Jijun Tang
ISSS
2002
IEEE
106views Hardware» more  ISSS 2002»
13 years 9 months ago
Modeling Assembly Instruction Timing in Superscalar Architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...