11 search results - page 2 / 3 » The Synthesis of a Hardware Scheduler for Non-Manifest Loops |
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
ISSS
1995
IEEE
13 years 8 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
DAC
2012
ACM
11 years 7 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...