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» The Validity of Retiming Sequential Circuits
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ASPDAC
2009
ACM
144views Hardware» more  ASPDAC 2009»
13 years 10 months ago
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis
Iterative retiming and resynthesis is a powerful way to optimize sequential circuits but its massive adoption has been hampered by the hardness of verification. This paper tackle...
Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee
FMCAD
2009
Springer
14 years 10 hour ago
Retiming and resynthesis with sweep are complete for sequential transformation
— There is a long history of investigations and debates on whether a sequence of retiming and resynthesis is complete for all sequential transformations (on steady states). It ha...
Hai Zhou
ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
14 years 2 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Preserving synchronizing sequences of sequential circuits after retiming
Abstract We propose a novel approach to preserve the synchronizing sequences of a circuit after retiming. The significance of this problem stems from the necessity of maintaining c...
Maher N. Mneimneh, Karem A. Sakallah, John Moondan...
ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
13 years 11 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf