We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative ...
Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelik...
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
We study the minimum-costbounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologi...
Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Alb...
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...