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ICCAD
1999
IEEE
132views Hardware» more  ICCAD 1999»
13 years 9 months ago
The associative-skew clock routing problem
We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative ...
Yu Chen, Andrew B. Kahng, Gang Qu, Alexander Zelik...
ASPDAC
2012
ACM
247views Hardware» more  ASPDAC 2012»
12 years 14 days ago
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
Xin Zhao, Sung Kyu Lim
DAC
1995
ACM
13 years 8 months ago
On the Bounded-Skew Clock and Steiner Routing Problems
We study the minimum-costbounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologi...
Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Alb...
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
13 years 6 months ago
Register placement for low power clock network
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qian...