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» The associative-skew clock routing problem
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ICCAD
2010
IEEE
141views Hardware» more  ICCAD 2010»
13 years 4 months ago
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
ICCAD
1995
IEEE
140views Hardware» more  ICCAD 1995»
13 years 9 months ago
Bounded-skew clock and Steiner routing under Elmore delay
: We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We presenttwo approachesto construct bounded-skew routing trees: (i) the Boundary Mergin...
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-...
ICCAD
1993
IEEE
123views Hardware» more  ICCAD 1993»
13 years 10 months ago
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
13 years 10 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
GECCO
2005
Springer
152views Optimization» more  GECCO 2005»
13 years 11 months ago
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
Guofang Nan, Minqiang Li, Jisong Kou