Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
: We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We presenttwo approachesto construct bounded-skew routing trees: (i) the Boundary Mergin...
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-...
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...