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CISIS
2009
IEEE
14 years 2 days ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
CCGRID
2004
IEEE
13 years 9 months ago
DWDM-RAM: a data intensive Grid service architecture enabled by dynamic optical networks
Next generation applications and architectures (for example, Grids) are driving radical changes in the nature of traffic, service models, technology, and cost, creating opportunit...
Tal Lavian, Joe Mambretti, Doug Cutrell, Howard J....
ISPD
2005
ACM
130views Hardware» more  ISPD 2005»
13 years 10 months ago
Improved algorithms for link-based non-tree clock networks for skew variability reduction
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
Anand Rajaram, David Z. Pan, Jiang Hu